An as simplestic as possible 8-bit Microprocessing architecture for RISA-MPD (Reprogrammable instruction set architecture for microprocessing devices). Based on first Revision of 6502 can be implementable on 74xx TTL. Comes with a custom and open source java based psudo-assembler.

An advanced varient of TMP8 Microprocessing architecture fully compatable with RISA-MPD and has more complex and flexible instruction set.

Implementation of 250nm 12T SRAM memory cell with Generic 250nm CMOS TSMC technology.

Implementation of RISA-MPD (Reprogrammable instruction set architecture - for microprocessing devices) on Generic 250nm CMOS TSMC technology.

Mathematical model of Binary Phase Shift Keying (BPSK) modulation and demodulation for low signal to noise ratio. Simulation demonstration of on MATLAB.

Model on Signal Processing to encrypt and decrypt multimedia using chaotic systems. As by using Logistic Map function and discrete cosine transform.