The TMP8 is an 8-bit parallel central processor unit a temporary and early development design for implementation of RISA-MPD(Reprogrammable Instruction Set Architecture for Microprocessing Devices).

The processor communicates over an 8-bit Data bus and a 4-bit Address bus. Since Processor is in early development stage it doesn"t have any external control lines for memory addressing but fully ISA driven design for memory management, 8-Bit Data can be transmitted between the CPU and external Memory between 0x0 to 0xF Address possibility.

This Architecture contains a total of four (4) 8-Bit Multipurpose Registers, an Instruction Register, three (3) General Purpose Registers named as X, Y and Z. Here Register-X is accumulator, Register-Z is output latch Register and Register-Y is for Register to Memory data communicator, an 8-Bit Binary Counter for addressing Memory through Memory Address Register (MAR).

The control portion of the architecture use programmed (Flashed) ISA to implement variety of register transfer, memory transfer, basic arithmetic control. All the instructions are coded in one byte (8 bits); Presently Immediate data load, RAM Reverse transfer is unavailable.

Input and Output are in binary format and not encoded or decoded on input or output operations.

The Instruction set of the TMP8 consists of 16 instructions including data manipulation, basic binary arithmetic, and jump

The normal program flow of TMP8 may be paused (HALT) using external inputs and Resettable using external inputs.

The four basic functional blocks of TMP8 processor are the Registers, Arithmetic logic unit, Memory, Instruction Set Architecture (Control Unit).

Instruction Register: - Instructions are fetched from memory, stored in the instruction register, and decoded for control of ALU, Memories or Data transfers, It also responsible for dividing instruction into opcode and operand (generally address for transfer functions).

1. Instruction Register: Stores 8-bit instruction in it fetched from ROM or RAM (DFT) specific.

2. Instruction Decoder: Accepts the incoming instruction form instructions register split it into opcode (Main instruction) and operand (additional address to be changed) and generates an address of 8-bit by decoding, that specific instruction is now ready to be execute.

3. Instruction Set: Accepts the Instruction address from instruction decoder and fetch the data (16-Bit Data line) from main instruction firmware memory for that instruction and control the inputs and outputs control of different components.